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19-3882; Rev 0; 10/05
2.2W Stereo Audio Power Amplifier with Analog Volume Control
General Description
The MAX9787 combines a stereo, 2.2W audio power amplifier with an analog volume control in a single device. A high 90dB PSRR and low 0.01% THD+N ensures clean, low-distortion amplification of the audio signal. The analog volume control can be driven with a potentiometer, an RC-filtered PWM source, or a DAC output. A BEEP input allows the addition of alert signals from the controller to the audio path. Industry-leading, click-and-pop suppression eliminates audible transients during power and shutdown cycles. Other features include single-supply voltage, a shutdown mode, logic-selectable gain, thermal-overload, and output short-circuit protection. The MAX9787 is offered in a space-saving, thermally efficient, 28-pin, thin QFN (5mm x 5mm x 0.8mm) package, and is specified over the extended -40C to +85C temperature range. Analog Volume Control BEEP Input with Glitch Filter 5V Single-Supply Operation High 90dB PSRR Low-Power Shutdown Mode Industry-Leading Click-and-Pop Suppression Low 0.01% THD+N at 1kHz Short-Circuit and Thermal Protection Selectable-Gain Settings Space-Saving 28-Pin TQFN (5mm x 5mm x 0.8mm)
Features
Class AB, 2.2W, Stereo BTL Speaker Amplifiers
MAX9787
Applications
Notebook PCs Flat-Panel TVs Tablet PCs PC Displays Portable DVD Players LCD Projectors Multimedia Monitors
PART MAX9787ETI+
Ordering Information
PIN-PACKAGE 28 TQFN-EP* PKG CODE T2855N-1
Note: This device is specified for -40C to +85C operation. +Denotes lead-free package. *EP = Exposed paddle.
Typical Operating Circuit
PGND BIAS
Pin Configuration
OUTRPVDD PVDD GND
TOP VIEW
+5V
21
20
19
18
OUTR+
17
16
15 14 13 12
N.C. N.C. VSS CPVSS C1N CPGND C1P

BEEP
SHDN GAIN2 GAIN1 VDD GND INR
22 23 24 25 26 27 28
*EP
MAX9787
11 10 9 8
MAX9787
VOLUME
VOL
+
1
INL
2
BEEP
3
PGND
4
OUTL+
5
OUTL-
6
PVDD
7
CPVDD
*EXPOSED PAD.
THIN QFN
________________________________________________________________ Maxim Integrated Products
1
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2.2W Stereo Audio Power Amplifier with Analog Volume Control MAX9787
ABSOLUTE MAXIMUM RATINGS
Supply Voltage (VDD, PVDD, CPVDD to GND) .......................+6V GND to PGND.....................................................................0.3V CPVSS, C1N, VSS to GND .........................-6.0V to (GND + 0.3V) Any Other Pin .............................................-0.3V to (VDD + 0.3V) Duration of OUT_ Short Circuit to GND or PVDD ........Continuous Duration of OUT_+ Short Circuit to OUT_- .................Continuous Continuous Current (PVDD, OUT_, PGND) ...........................1.7A Continuous Current (CPVDD, C1N, C1P, CPVSS, VSS)......850mA Continuous Input Current (all other pins) .........................20mA Continuous Power Dissipation (TA = +70C) 28-Pin Thin QFN (derate 23.8mW/C above +70C) .......1.9W Junction Temperature ......................................................+150C Operating Temperature Range ...........................-40C to +85C Storage Temperature Range .............................-65C to +150C Lead Temperature (soldering, 10s) .................................+300C
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(V DD = PV DD = CPV DD = 5V, GND = PGND = CPGND = 0V, SHDN = V DD , C BIAS = 1F, C1 = C2 = 1F, speaker load terminated between OUT_+ and OUT_-, GAIN1 = GAIN2 = VOL = 0V, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25C.) (Note 1)
PARAMETER GENERAL Supply Voltage Range Quiescent Supply Current Shutdown Supply Current Bias Voltage Switching Time Input Resistance Turn-On Time Output Offset Voltage Power-Supply Rejection Ratio (Note 3) VDD, PVDD IDD ISHDN VBIAS tSW RIN tSON VOS Measured between OUT_+ and OUT_-, TA = +25C PVDD or VDD = 4.5V to 5.5V (TA = +25C) PSRR f = 1kHz, VRIPPLE = 200mVP-P f = 10kHz, VRIPPLE = 200mVP-P Output Power (Note 4) Total Harmonic Distortion Plus Noise POUT THD+N = 1%, f = 1kHz, TA = +25C RL = 8 RL = 4 RL = 3 0.65 1.2 75 Gain or input switching Amplifier inputs (Note 2) 10 SHDN = GND 1.7 Inferred from PSRR test 4.5 14 0.2 1.8 10 20 25 0.4 90 80 55 0.8 1.5 2.2 0.01 0.02 % W dB 6 30 5.5 29 5 1.9 V mA A V s k ms mV SYMBOL CONDITIONS MIN TYP MAX UNITS
THD+N
RL = 8, POUT = 500mW, f = 1kHz RL = 4, POUT = 1W, f = 1kHz
2
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2.2W Stereo Audio Power Amplifier with Analog Volume Control
ELECTRICAL CHARACTERISTICS (continued)
(V DD = PV DD = CPV DD = 5V, GND = PGND = CPGND = 0V, SHDN = V DD , C BIAS = 1F, C1 = C2 = 1F, speaker load terminated between OUT_+ and OUT_-, GAIN1 = GAIN2 = VOL = 0V, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25C.) (Note 1)
PARAMETER Signal-to-Noise Ratio Noise Capacitive-Load Drive Crosstalk Slew Rate SR GAIN1 = 0, GAIN2 = 0 Gain (Maximum Volume Setting) AVMAX(SPKR) GAIN1 = 1, GAIN2 = 0 GAIN1 = 0, GAIN2 = 1 GAIN1 = 1, GAIN2 = 1 CHARGE PUMP Charge-Pump Frequency VOLUME CONTROL VOL Input Impedance VOL Input Hysteresis Full-Mute Input Voltage Channel Matching BEEP INPUT Beep Signal Minimum Amplitude Beep Signal Minimum Frequency Logic Input High Voltage Logic Input Low Voltage Logic Input Current VBEEP fBEEP VIH VIL IIN RB = 33k (Note 6) 0.3 300 2 0.8 1 VP-P Hz V V A (Note 5) AV = -25dB to +13.5dB RVOL 100 10 4.29 0.2 M mV V dB fOSC 500 550 600 kHz SYMBOL SNR Vn CL CONDITIONS RL = 8, POUT = 500mW, BW = 22Hz to 22kHz BW = 22Hz to 22kHz, A-weighted No sustained oscillations L to R, R to L, f = 10kHz MIN TYP 90 80 200 75 1.4 6 7.5 9 10.5 dB MAX UNITS dB VRMS pF dB V/s
MAX9787
LOGIC INPUT (SHDN, GAIN1, GAIN2, VOL)
Note 1: Note 2: Note 3: Note 4: Note 5: Note 6:
All devices are 100% production tested at room temperature. All temperature limits are guaranteed by design. Guaranteed by design. Not production tested. PSRR is specified with the amplifier input connected to GND through CIN. Output power levels are measured with the thin QFN's exposed paddle soldered to the ground plane. See Table 3 for details of the mute levels. The value of RB dictates the minimum beep signal amplitude (see the BEEP Input section).
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2.2W Stereo Audio Power Amplifier with Analog Volume Control MAX9787
Typical Operating Characteristics
(Measurement BW = 22Hz to 22kHz, TA = +25C, unless otherwise noted.)
TOTAL HARMONIC DISTORTION PLUS NOISE vs. FREQUENCY
MAX9787 toc01
TOTAL HARMONIC DISTORTION PLUS NOISE vs. FREQUENCY
MAX9787 toc02
TOTAL HARMONIC DISTORTION PLUS NOISE vs. FREQUENCY
VCC = 5V RL = 8 AV = 10.5dB OUTPUT POWER = 100mW
MAX9787 toc03
10
1
VCC = 5V RL = 3 AV = 10.5dB OUTPUT POWER = 1.5W
10
1
VCC = 5V RL = 4 AV = 10.5dB OUTPUT POWER = 1.25W
10
1
THD+N (%)
THD+N (%)
0.1
0.1
THD+N (%)
0.1
0.01 OUTPUT POWER = 500mW 0.001
0.01 OUTPUT POWER = 500mW 0.001
0.01 OUTPUT POWER = 600mW 0.001
0.0001 10 100 1k FREQUENCY (Hz) 10k 100k
0.0001 10 100 1k FREQUENCY (Hz) 10k 100k
0.0001 10 100 1k FREQUENCY (Hz) 10k 100k
TOTAL HARMONIC DISTORTION PLUS NOISE vs. OUTPUT POWER
MAX9787 toc04
TOTAL HARMONIC DISTORTION PLUS NOISE vs. OUTPUT POWER
MAX9787 toc05
TOTAL HARMONIC DISTORTION PLUS NOISE vs. OUTPUT POWER
VCC = 5V RL = 8 AV = 10.5dB
MAX9787 toc06
100 VCC = 5V RL = 3 AV = 10.5dB
100
10
10
VCC = 5V RL = 4 AV = 10.5dB
100
10
THD+N (%)
THD+N (%)
1 fIN = 10kHz 0.1
THD+N (%)
1 fIN = 10kHz 0.1
1
0.1
fIN = 10kHz
0.01 fIN = 20Hz 0.001 0 0.5 1.0 1.5 2.0 2.5 3.0 OUTPUT POWER (W) fIN = 1kHz
0.01 fIN = 20Hz 0.001 0 0.5 1.0 1.5 OUTPUT POWER (W) 2.0 fIN = 1kHz
0.01 fIN = 20Hz 0.001 0 0.2 0.4 0.6 0.8 OUTPUT POWER (W) 1.0 1.2 fIN = 1kHz
OUTPUT POWER vs. LOAD RESISTANCE
MAX9787 toc07
POWER DISSIPATION vs. OUTPUT POWER
MAX9787 toc08
3.0 2.5 OUTPUT POWER (W) 2.0 THD+N = 10% 1.5 1.0 0.5 0 1 10 LOAD RESISTANCE () THD+N = 1% VCC = 5V f = 1kHz AV = 10.5dB
5 VDD = 5V f = 1kHz POUT = POUTL + POUTR RL = 4
POWER DISSIPATION (W)
4
3
2 RL = 8
1
0 100 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 OUTPUT POWER (W)
4
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2.2W Stereo Audio Power Amplifier with Analog Volume Control MAX9787
Typical Operating Characteristics (continued)
(Measurement BW = 22Hz to 22kHz, TA = +25C, unless otherwise noted.)
POWER-SUPPLY REJECTION RATIO vs. FREQUENCY
MAX9787 toc09
CROSSTALK vs. FREQUENCY
-10 -20 CROSSTALK (dB) -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 VCC = 5V VRIPPLE = 200mVP-P RL = 4
MAX9787 toc10
0 -10 -20 -30 PSRR (dB) -40 -50 -60 -70 -80 -90 -100 10
VRIPPLE = 200mVP-P AV = 10.5dB OUTPUT REFERRED
0
LEFT TO RIGHT RIGHT TO LEFT
100
1k FREQUENCY (Hz)
10k
100k
10
100
1k FREQUENCY (Hz)
10k
100k
TURN-ON RESPONSE
MAX9787 toc11
TURN-OFF RESPONSE
MAX9787 toc12
5V/div SHDN OUT_+ AND OUT_SHDN OUT_+ AND OUT_-
5V/div
2V/div
2V/div
OUT_+ - OUT_RL = 8 20ms/div
100mV/div
OUT_+ - OUT_RL = 8 20ms/div
20mV/div
SUPPLY CURRENT vs. SUPPLY VOLTAGE
16 SUPPLY CURRENT (mA) 14 12 10 8 6 4 2 0 4.50 4.75 5.00 5.25 5.50 SUPPLY VOLTAGE (V) 0.05 0 4.50
MAX9787 toc13
SHUTDOWN SUPPLY CURRENT vs. SUPPLY VOLTAGE
MAX9787 toc14
18
0.35 0.30 SUPPLY CURRENT (A) 0.25 0.20 0.15 0.10
4.75
5.00
5.25
5.50
SUPPLY VOLTAGE (V)
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2.2W Stereo Audio Power Amplifier with Analog Volume Control MAX9787
Pin Description
PIN 1 2 3, 19 4 5 6, 15, 16 7 8 9 10 11 12 13, 14 17 18 20, 26 21 22 23 24 25 27 28 EP NAME INL BEEP PGND OUTL+ OUTLPVDD CPVDD C1P CPGND C1N CPVSS VSS N.C. OUTROUTR+ GND BIAS SHDN GAIN2 GAIN1 VDD INR VOL EP Left-Channel Audio Input Audible Alert Beep Input Power Ground Left-Channel Positive Speaker Output Left-Channel Negative Speaker Output Speaker Amplifier Power Supply Charge-Pump Power Supply Charge-Pump Flying-Capacitor Positive Terminal Charge-Pump Ground Charge-Pump Flying-Capacitor Negative Terminal Charge-Pump Output. Connect to VSS. Amplifier Negative Power Supply No Connection. Not internally connected. Right-Channel Negative Speaker Output Right-Channel Positive Speaker Output Ground Common-Mode Bias Voltage. Bypass with a 1F capacitor to GND. Shutdown. Drive SHDN low to disable the device. Connect SHDN to VDD for normal operation. Gain Control Input 2 Gain Control Input 1 Power Supply Right-Channel Audio Input Analog Volume Control Input Exposed Pad. Connect to GND. FUNCTION
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2.2W Stereo Audio Power Amplifier with Analog Volume Control
Detailed Description
The MAX9787 combines a 2.2W bridge-tied load (BTL) speaker amplifier and an analog volume control, BEEP input, and four-level gain control. The MAX9787 features high 90dB, low 0.01% THD+N, industry-leading clickpop performance, and a low-power shutdown mode. Each signal path consists of an input amplifier that sets the gain of the signal path, and feeds the speaker amplifier (Figure 1). The speaker amplifier uses a BTL architecture, doubling the voltage drive to the speakers and eliminating the need for DC-blocking capacitors. The output consists of two signals, identical in magnitude, but 180o out of phase. An analog volume control varies the gain of the amplifiers based on the DC voltage applied at VOL. An undervoltage lockout prevents operation from an insufficient power supply. Click-and-pop suppression eliminates audible transients on startup and shutdown. The amplifiers include thermal-overload and short-circuit protection. An additional feature of the speaker amplifiers is that there is no phase inversion from input to output. Charge Pump The MAX9787 features a low-noise charge pump. The 550kHz switching frequency is well beyond the audio range, and does not interfere with the audio signals. The switch drivers feature a controlled switching speed that minimizes noise generated by turn-on and turn-off transients. Limiting the switching speed of the charge pump minimizes the di/dt noise caused by the parasitic bond wire and trace inductance. Although not typically required, additional high-frequency ripple attenuation can be achieved by increasing the size of C2 (see the Typical Operating Circuit).
MAX9787
BIAS
The MAX9787 features an internally generated, powersupply independent, common-mode bias voltage of 1.8V referenced to GND. BIAS provides both click-and-pop suppression and sets the DC bias level for the amplifiers. Choose the value of the bypass capacitor as described in the BIAS Capacitor section. No external load should be applied to BIAS. Any load lowers the BIAS voltage, affecting the overall performance of the device.
Gain Selection
The GAIN1 and GAIN2 inputs set the maximum gain of the speaker and amplifiers (Table 1). The gain of the device can vary based upon the voltage at VOL (see the Analog Volume Control section). However, the maximum gain cannot be exceeded.
Analog Volume Control (VOL)
An analog volume control varies the gain of the device in 31 discrete steps based upon the DC voltage applied to VOL. The input range of VVOL is from 0 (full volume) to 0.858 x PVDD (full mute), with example step sizes shown in Table 2. Connect the reference of the device driving VOL (Figure 2) to PVDD. Since the volume control ADC is ratiometric to PVDD, any changes in
Table 1. Gain Settings
GAIN2 0 0 GAIN1 0 1 0 1 SPEAKER MODE GAIN (dB) 6 7.5 9 10.5
IN_
1 1
BIAS BIAS
OUT_+
MAX9787 PVDD
VOL
VOLUME CONTROL
OUT_ BIAS
VREF DAC VOL
Figure 1. MAX9787 Signal Path
Figure 2. Volume Control Circuit 7
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2.2W Stereo Audio Power Amplifier with Analog Volume Control MAX9787
Table 2. Volume Levels
VVOL (V) VMIN* 0 0.742 0.860 0.977 1.094 1.211 1.328 1.446 1.563 1.680 1.797 1.914 2.032 2.149 2.266 2.383 2.500 2.617 2.735 2.852 2.969 3.086 3.203 3.321 3.438 3.555 3.672 3.789 3.907 4.024 4.141 4.258 VTYP* 0.370 0.800 0.915 1.035 1.150 1.265 1.385 1.500 1.620 1.735 1.855 1.970 2.090 2.205 2.320 2.440 2.555 2.675 2.790 2.910 3.025 3.140 3.260 3.375 3.495 3.610 3.730 3.845 3.965 4.080 4.195 4.290 VMAX* 0.742 0.860 0.977 1.094 1.211 1.328 1.446 1.563 1.680 1.797 1.914 2.032 2.149 2.266 2.383 2.500 2.617 2.735 2.852 2.969 3.086 3.203 3.321 3.438 3.555 3.672 3.789 3.907 4.024 4.141 4.258 5.000 GAIN1 = 0, GAIN2 = 0 6 5 4 3 1 -1 -3 -5 -7 -9 -11 -13 -15 -17 -19 -21 -23 -25 -27 -29 -31 -33 -35 -37 -41 -45 -48 -53 -57 -61 -65 MUTE SPEAKER MODE GAIN (dB) GAIN1 = 1, GAIN2 = 0 7.5 7 6 5 4 3 1 -1 -3 -5 -7 -9 -11 -13 -15 -17 -19 -21 -23 -25 -27 -29 -31 -3 -35 -37 -41 -45 -49 -53 -57 MUTE GAIN1 = 0, GAIN2 = 1 9 8.5 8 7.5 7 6 5 4 3 1 -1 -3 -5 -7 -9 -11 -13 -15 -17 -9 -21 -23 -2 -27 -29 -31 -33 -35 -37 -41 -45 MUTE GAIN1 = 1, GAIN2 = 1 10.5 10 9.5 9 8.5 8 7.5 7 6 5 4 3 1 -1 -3 -5 -7 -9 -11 -13 -15 -17 -19 -21 -23 -25 -27 -29 -31 -33 -35 MUTE
*Based on PVDD = 5V
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2.2W Stereo Audio Power Amplifier with Analog Volume Control
PVDD are negated. The gain step sizes are not constant; the step sizes are 0.5dB/step at the upper extreme, 2dB/step in the midrange, and 4dB/step at the lower extreme. Figure 3 shows the transfer function of the volume control for a 5V supply. roughly the amplitude of VBEEP(OUT) times the gain of the selected signal path. The input resistor (RB) sets the gain of the BEEP input amplifier, and thus the amplitude of V BEEP(OUT) . Choose RB based on: RB VIN x RINT 0.3
MAX9787
BEEP Input
An audible alert beep input (BEEP) accepts a mono system alert signal and mixes it into the stereo audio path. When the amplitude of V BEEP(OUT) exceeds 800mVP-P (Figure 4) and the frequency of the beep signal is greater than 400Hz, the beep signal is mixed into the active audio path (speaker or headphone). If the signal at VBEEP(OUT) is either < 800mVP-P or <400Hz, the BEEP signal is not mixed into the audio path. The amplitude of the BEEP signal at the device output is
VOLUME CONTROL TRANSFER FUNCTION
20 10 0 -10 GAIN (dB) -20 -30 -40 -50 -60 -70 -80 0 1 2 VVOL (V) 3 4 5 MAX9787 GAIN1 = GAIN2 = 0 AUDIO TAPER POT
where RINT is the value of the BEEP amplifier feedback resistor (47k) and VIN is the BEEP input amplitude. Note that the BEEP amplifier can be set up as either an attenuator, if the original alert signal amplitude is too large, or set to gain up the alert signal if it is below 800mVP-P. AC-couple the alert signal to BEEP. Choose the value of the coupling capacitor as described in the Input Filtering section. Multiple beep inputs can be summed (Figure 4).
Shutdown
The MAX9787 features a 0.2A, low-power shutdown mode that reduces quiescent current consumption and extends battery life. Driving SHDN low disables the drive amplifiers, bias circuitry, and charge pump, and drives BIAS and all outputs to GND. Connect SHDN to VDD for normal operation.
Click-and-Pop Suppression
The MAX9787 speaker amplifiers feature Maxim's comprehensive, industry-leading click-and-pop suppression. During startup, the click-and-pop suppression circuitry eliminates any audible transient sources internal to the device. When entering shutdown, both amplifier outputs ramp to GND quickly and simultaneously.
Figure 3. Volume Control Transfer Function
RS1 47k RINT 47k 0.47F SOURCE 2 0.47F SOURCE 3 RS3 47k BEEP VOUT(BEEP) RS2 47k SPEAKER AMPLIFIER INPUTS
0.47F SOURCE 1
WINDOW DETECTOR (0.3VP-P THRESHOLD) BIAS FREQUENCY DETECTOR (300Hz THRESHOLD) MAX9787
Figure 4. Beep Input _______________________________________________________________________________________ 9
2.2W Stereo Audio Power Amplifier with Analog Volume Control MAX9787
Applications Information
BTL Speaker Amplifiers
The MAX9787 features speaker amplifiers designed to drive a load differentially, a configuration referred to as bridge-tied load (BTL). The BTL configuration (Figure 5) offers advantages over the single-ended configuration, where one side of the load is connected to ground. Driving the load differentially doubles the output voltage compared to a single-ended amplifier under similar conditions. Thus, the device's differential gain is twice the closed-loop gain of the input amplifier. The effective gain is given by: A VD = 2 x RF RIN
Power Dissipation and Heat Sinking
Under normal operating conditions, the MAX9787 can dissipate a significant amount of power. The maximum power dissipation for each package is given in the Absolute Maximum Ratings under Continuous Power Dissipation, or can be calculated by the following equation: PDISSPKG(MAX) = TJ(MAX) - TA JA
where TJ(MAX) is +150C, TA is the ambient temperature, and JA is the reciprocal of the derating factor in oC/W as specified in the Absolute Maximum Ratings section. For example, JA of the TQFN package is +42oC/W. For optimum power dissipation, the exposed paddle of the package should be connected to the ground plane (see the Layout and Grounding section). For 8 applications, the worst-case power dissipation occurs when the output power is 1.1W/channel, resulting in a power dissipation of about 1W. In this case, the TQFN packages can be used without violating the maximum power dissipation or exceeding the thermal protection threshold.
Substituting 2 X VOUT(P-P) into the following equation yields four times the output power due to double the output voltage: VRMS = VOUT(P-P) 22
2 V POUT = RMS RL
Output Power
The increase in power delivered by the BTL configuration directly results in an increase in internal power dissipation over the single-ended configuration. If the power dissipation for a given application exceeds the maximum allowed for a given package, either reduce VDD, increase load impedance, decrease the ambient temperature, or add heatsinking to the device. Large output, supply, and ground PC board traces improve the maximum power dissipation in the package.
1000 100 VDD = 5V RL = 16 AV = 3dB
Since the differential outputs are biased at midsupply, there is no net DC voltage across the load. This eliminates the need for DC-blocking capacitors required for single-ended amplifiers. These capacitors can be large and expensive, can consume board space, and can degrade low-frequency performance.
+1
VOUT(P-P)
THD+N (%)
10 OUTPUTS IN PHASE 1 0.1
2 x VOUT(P-P)
-1
VOUT(P-P)
0.01 0.001 0 25
OUTPUTS 180 OUT OF PHASE 50 75 100 125 150
OUTPUT POWER (mW)
Figure 5. Bridge-Tied Load Configuration
Figure 6. Total Harmonic Distortion Plus Noise vs. Output Power with Inputs In/Out of Phase
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2.2W Stereo Audio Power Amplifier with Analog Volume Control MAX9787
Table 3. Suggested Capacitor Manufacturers
SUPPLIER Taiyo Yuden TDK PHONE 800-348-2496 807-803-6100 FAX 847-925-0899 847-390-4405 WEBSITE www.t-yuden.com www.component.tdk.com
Thermal-overload protection limits total power dissipation in these devices. When the junction temperature exceeds +160C, the thermal-protection circuitry disables the amplifier output stage. The amplifiers are enabled once the junction temperature cools by 15C. This results in a pulsing output under continuous thermal-overload conditions as the device heats and cools.
Power Supplies
The MAX9787 speaker amplifiers are powered from PVDD. PVDD ranges from 4.5V to 5.5V. VSS is the negative supply of the amplifiers. Connect VSS to CPVSS. The charge pump is powered by CPVDD. CPVDD should be the same potential as PVDD. The charge pump inverts the voltage at CPV DD , and the resulting voltage appears at CPVSS. The remainder of the device is powered by VDD.
BIAS Capacitor BIAS is the output of the internally generated DC bias voltage. The BIAS bypass capacitor, CBIAS, improves PSRR and THD+N by reducing power supply and other noise sources at the common-mode bias node, and also generates the clickless/popless, startup/shutdown DC bias waveforms for the speaker amplifiers. Bypass BIAS with a 1F capacitor to GND. Charge-Pump Capacitor Selection Use capacitors with an ESR less than 100m for optimum performance. Low-ESR ceramic capacitors minimize the output resistance of the charge pump. For best performance over the extended temperature range, select capacitors with an X7R dielectric. Table 4 lists suggested manufacturers. Flying Capacitor (C1) The value of the flying capacitor (C1) affects the load regulation and output resistance of the charge pump. A C1 value that is too small degrades the device's ability to provide sufficient current drive, which leads to a loss of output voltage. Increasing the value of C1 improves load regulation and reduces the charge-pump output resistance to an extent. See the Output Power vs. Charge-Pump Capacitance and Load Resistance graph in the Typical Operating Characteristics. Above 2.2F, the on-resistance of the switches and the ESR of C1 and C2 dominate. Output Capacitor (C2) The output capacitor value and ESR directly affect the ripple at CPVSS. Increasing the value of C2 reduces output ripple. Likewise, decreasing the ESR of C2 reduces both ripple and output resistance. Lower capacitance values can be used in systems with low maximum output power levels. See the Output Power vs. Charge-Pump Capacitance and Load Resistance graph in the Typical Operating Characteristics.
Component Selection
Input Filtering The input capacitor (CIN), in conjunction with the amplifier input resistance (RIN), forms a highpass filter that removes the DC bias from an incoming signal (see the Typical Operating Circuit). The AC-coupling capacitor allows the amplifier to bias the signal to an optimum DC level. Assuming zero source impedance, the -3dB point of the highpass filter is given by: f-3dB = 1 2RINCIN
R IN is the amplifier's internal input resistance value given in the Electrical Characteristics. Choose CIN such that f-3dB is well below the lowest frequency of interest. Setting f-3dB too high affects the amplifier's low-frequency response. Use capacitors with low-voltage coefficient dielectrics, such as tantalum or aluminum electrolytic. Capacitors with high-voltage coefficients, such as ceramics, may result in increased distortion at low frequencies.
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2.2W Stereo Audio Power Amplifier with Analog Volume Control MAX9787
CPVDD Bypass Capacitor The CPVDD bypass capacitor (C3) lowers the output impedance of the power supply and reduces the impact of the MAX9787's charge-pump switching transients. Bypass CPVDD with C3, the same value as C1, and place it physically close to the CPVDD and PGND (refer to the MAX9750 Evaluation Kit for a suggested layout). audio signal. Connect CPGND, PGND, and GND together at a single point on the PC board. Route CPGND and all traces that carry switching transients away from GND, PGND, and the traces and components in the audio signal path. Connect all components associated with the charge pump (C2 and C3) to the CPGND plane. Connect VSS and CPVSS together at the device. Place the chargepump capacitors (C1, C2, and C3) as close to the device as possible. Bypass PVDD with a 0.1F capacitor to GND. Place the bypass capacitors as close to the device as possible. Use large, low-resistance output traces. As load impedance decreases, the current drawn from the device outputs increase. At higher current, the resistance of the output traces decrease the power delivered to the load. For example, when compared to a 0 trace, a 100m trace reduces the power delivered to a 4 load from 2.1W to 2W. Large output, supply, and GND traces also improve the power dissipation of the device. The MAX9787 thin QFN features and exposed thermal pad on its underside. This pad lowers the package's thermal resistance by providing a direct heat conduction path from the die to the PC board. Connect the exposed thermal pad to GND by using a large pad and multiple vias to the GND plane.
Powering Other Circuits from a Negative Supply
An additional benefit of the MAX9787 is the internally generated negative supply voltage (CPVSS). CPVSS provides the negative supply for the amplifiers. It can also be used to power other devices within a design. Current draw from CPV SS should be limited to 5mA; exceeding this affects the operation of the amplifier. A typical application is a negative supply to adjust the contrast of LCD modules. When considering the use of CPVSS in this manner, note that the charge-pump voltage of CPVSS is roughly proportional to PVDD and is not a regulated voltage. The charge-pump output impedance plot appears in the Typical Operating Characteristics.
Layout and Grounding
Proper layout and grounding are essential for optimum performance. Use large traces for the power-supply inputs and amplifier outputs to minimize losses due to parasitic trace resistance, as well as route head away from the device. Good grounding improves audio performance, minimizes crosstalk between channels, and prevents any switching noise from coupling into the
Chip Information
TRANSISTOR COUNT: 9591 PROCESS: BiCMOS
12
______________________________________________________________________________________
2.2W Stereo Audio Power Amplifier with Analog Volume Control
Block Diagram
MAX9787
4.5V TO 5.5V
0.1F VDD 25 6, 15, 16 PVDD MAX9787 CIN 1F LEFT-CHANNEL AUDIO INPUT 4 OUTL+ BTL AMPLIFIER 5 OUTL4.5V TO 5.5V 0.1F
INL 1
GAIN/ VOLUME CONTROL
CIN 1F RIGHT-CHANNEL AUDIO INPUT
INR 27
GAIN/ VOLUME CONTROL
18 OUTR+ BTL AMPLIFIER 17 OUTR-
BIAS 21 CBIAS 1F VOL 28 VDD GAIN1 24 VDD GAIN2 23 1F 47k BEEP 2 VDD SHDN 22 3V TO 5.5V 1F C1 1F C1N CPGND 9 11 CPVSS 12 VSS C2 1F 20, 26 GND 3, 19 PGND CPVDD 7 C1P 8 10 CHARGE PUMP GAIN/ VOLUME CONTROL HEADPHONE DETECTION BEEP DETECTION SHUTDOWN CONTROL
______________________________________________________________________________________
13
2.2W Stereo Audio Power Amplifier with Analog Volume Control MAX9787
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/packages.)
D2 D D/2 MARKING k L E/2 E2/2 E (NE-1) X e
C L C L
b D2/2
0.10 M C A B
AAAAA
E2
PIN # 1 I.D.
DETAIL A
e (ND-1) X e
e/2
PIN # 1 I.D. 0.35x45 DETAIL B
e
L1
L
C L
C L
L
L
e 0.10 C A 0.08 C
e
C
A1 A3
PACKAGE OUTLINE, 16, 20, 28, 32, 40L THIN QFN, 5x5x0.8mm
-DRAWING NOT TO SCALE-
21-0140
I
1
2
14
______________________________________________________________________________________
QFN THIN.EPS
2.2W Stereo Audio Power Amplifier with Analog Volume Control
Package Information (continued)
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/packages.)
MAX9787
COMMON DIMENSIONS
PKG. 16L 5x5 20L 5x5 28L 5x5 32L 5x5 40L 5x5 SYMBOL MIN. NOM. MAX. MIN. NOM. MAX. MIN. NOM. MAX. MIN. NOM. MAX. MIN. NOM. MAX.
EXPOSED PAD VARIATIONS PKG. CODES
D2
MIN. NOM. MAX.
E2
MIN. NOM. MAX.
exceptions
L
0.15
A A1 A3 b D E e k L
0.70 0.75 0.80 0.70 0.75 0.80 0.70 0.75 0.80 0.70 0.75 0.80 0.70 0.75 0.80 0 0.02 0.05 0 0.02 0.05 0 0.02 0.05 0 0.02 0.05 0 0.02 0.05 0.20 REF. 0.20 REF. 0.20 REF. 0.20 REF. 0.20 REF. 0.25 0.30 0.35 0.25 0.30 0.35 0.20 0.25 0.30 0.20 0.25 0.30 0.15 0.20 0.25 4.90 5.00 5.10 4.90 5.00 5.10 4.90 5.00 5.10 4.90 5.00 5.10 4.90 5.00 5.10 4.90 5.00 5.10 4.90 5.00 5.10 4.90 5.00 5.10 4.90 5.00 5.10 4.90 5.00 5.10 0.65 BSC. 0.50 BSC. 0.50 BSC. 0.40 BSC. 0.80 BSC.
DOWN BONDS ALLOWED
- 0.25 - 0.25 - 0.25 0.35 0.45 0.25 - 0.25 0.30 0.40 0.50 0.45 0.55 0.65 0.45 0.55 0.65 0.30 0.40 0.50 0.40 0.50 0.60 L1 0.30 0.40 0.50 40 N 20 28 32 16 ND 10 5 7 8 4 10 5 7 8 4 NE ----WHHC WHHD-1 WHHD-2 WHHB JEDEC
NOTES: 1. DIMENSIONING & TOLERANCING CONFORM TO ASME Y14.5M-1994. 2. ALL DIMENSIONS ARE IN MILLIMETERS. ANGLES ARE IN DEGREES. 3. N IS THE TOTAL NUMBER OF TERMINALS. 4. THE TERMINAL #1 IDENTIFIER AND TERMINAL NUMBERING CONVENTION SHALL CONFORM TO JESD 95-1 SPP-012. DETAILS OF TERMINAL #1 IDENTIFIER ARE OPTIONAL, BUT MUST BE LOCATED WITHIN THE ZONE INDICATED. THE TERMINAL #1 IDENTIFIER MAY BE EITHER A MOLD OR MARKED FEATURE. 5. DIMENSION b APPLIES TO METALLIZED TERMINAL AND IS MEASURED BETWEEN 0.25 mm AND 0.30 mm FROM TERMINAL TIP.
T1655-2 3.00 T1655-3 3.00 T1655N-1 3.00 T2055-3 3.00 3.00 T2055-4 T2055-5 3.15 T2855-3 3.15 T2855-4 2.60 T2855-5 2.60 3.15 T2855-6 T2855-7 2.60 T2855-8 3.15 T2855N-1 3.15 T3255-3 3.00 T3255-4 3.00 T3255-5 3.00 T3255N-1 3.00 T4055-1 3.20
3.10 3.10 3.10 3.10 3.10 3.25 3.25 2.70 2.70 3.25 2.70 3.25 3.25 3.10 3.10 3.10 3.10 3.30
3.20 3.20 3.20 3.20 3.20 3.35 3.35 2.80 2.80 3.35 2.80 3.35 3.35 3.20 3.20 3.20 3.20 3.40
3.00 3.00 3.00 3.00 3.00 3.15 3.15 2.60 2.60 3.15 2.60 3.15 3.15 3 3.00 3 3.00 3.00 3.00 3.20
3.10 3.10 3.10 3.10 3.10 3.25 3.25 2.70 2.70 3.25 2.70 3.25 3.25 3.10 3.10 3.10 3.10 3.30
3.20 3.20 3.20 3.20 3.20 3.35 3.35 2.80 2.80 3.35 2.80 3.35 3.35 .20 .20 3.20 3.20 3.40
** ** ** ** ** 0.40 ** ** ** ** ** 0.40 ** ** ** ** ** **
YES NO NO YES NO YES YES YES NO NO YES YES NO YES NO YES NO YES
** SEE COMMON DIMENSIONS TABLE
6. ND AND NE REFER TO THE NUMBER OF TERMINALS ON EACH D AND E SIDE RESPECTIVELY. 7. DEPOPULATION IS POSSIBLE IN A SYMMETRICAL FASHION. 8. COPLANARITY APPLIES TO THE EXPOSED HEAT SINK SLUG AS WELL AS THE TERMINALS. 9. DRAWING CONFORMS TO JEDEC MO220, EXCEPT EXPOSED PAD DIMENSION FOR T2855-3 AND T2855-6. 10. WARPAGE SHALL NOT EXCEED 0.10 mm. 11. MARKING IS FOR PACKAGE ORIENTATION REFERENCE ONLY. 12. NUMBER OF LEADS SHOWN ARE FOR REFERENCE ONLY. 13. LEAD CENTERLINES TO BE AT TRUE POSITION AS DEFINED BY BASIC DIMENSION "e", 0.05.
PACKAGE OUTLINE, 16, 20, 28, 32, 40L THIN QFN, 5x5x0.8mm
-DRAWING NOT TO SCALE-
21-0140
I
2
2
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 15 (c) 2005 Maxim Integrated Products
Heaney
Printed USA
is a registered trademark of Maxim Integrated Products, Inc.

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